CAUSE: | In a Verilog Design File (.v) at the specified location, a hexadecimal constant value contains illegal characters, that is, characters other than 0..9 , a..f , x , or z . |
ACTION: | Make sure the constant value contains only 0..9 , a..f , x , or z characters. |
See also:
Section 2.5 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual
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