| CAUSE: | In a Macro Definition Verilog Design File (.v) at the specified location, you specified parameters for the macro, but the parameters are not legal parameters. |
| ACTION: | Make sure you use legal characters and correct syntax for variables, numbers, and other text in the macro parameters. |
See also:
Section 19.3 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual
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