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Verilog HDL Compiler Directive error at <location>: incorrect use of predefined text macro <name> -- expected macro field <text>

CAUSE: In a Verilog Design File (.v) at the specified location, you used a recognized Compiler Directive (such as `define); however, the remaining syntax for the Compiler Directive is incorrect. As a result, Integrated Synthesis could not parse the specified macro field.
ACTION: Edit the design to make sure the correct syntax is used in the Compiler Directive and in the text macro field.

See also:

Section 19.3 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

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