Quartus

Verilog HDL syntax error at <location>: illegal character in octal constant value

CAUSE: In a Verilog Design File (.v) at the specified location, the specified octal constant value contains one or more illegal characters, that is, characters other than 0..7, x, or z.
ACTION: Make sure the octal constant value contains only 0..7, x, or z characters.

See also:

Section 2.5 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

- PLDWorld -

 
Created by chm2web html help conversion utility.