Quartus

Verilog HDL syntax error at <location>: illegal character <character> in user-defined primtive table

CAUSE: In a Verilog Design File (.v) at the specified location, you used a User-Defined Primitive (UDP) Declaration; however, the UDP table contains one or more illegal characters.
ACTION: Make sure the UDP table contains no illegal characters.

See also:

Section 8 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

- PLDWorld -

 
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