Quartus

Verilog HDL error at <location>: memory size reaches 2**<number> bits limit

CAUSE: In a Verilog Design File (.v) at the specified location, you specified a memory size; however, the memory size you specified is greater than or equal to the limit of 2**28 bits.
ACTION: Reduce the memory size to less than 2**28 bits.

See also:

Section 3.10.3 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

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