Quartus

Verilog HDL syntax error at <location>: vector size reaches 2**<number> bits limit

CAUSE: In a Verilog Design File (.v) at the specified location, you used the specified vector size, which is greater than or equal to the limit of 2**20 bits.
ACTION: Reduce the vector size to less than 2**20 bits.

See also:

Sections 3.3 and 3.10 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

- PLDWorld -

 
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