Quartus

Verilog HDL error at <location>: can't find port <name>

CAUSE: In a Verilog Design File (.v) at the specified location, you referenced the specified port, but that port name does not exist in the list of ports for the Module Definition.
ACTION: Make sure the port name reference matches the port name specified in the list of ports for the Module Definition.

See also:

Section 12.1 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

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