| CAUSE: | You tried to create a symbol for the specified Verilog Design File (.vhd), but the Verilog Design File has a Port Declaration that is a multidimensional array type. The Quartus II sofware cannot create a symbol for a module with a multidimensional array type. |
| ACTION: | Change the port types of the Verilog HDL module to be simple ports or one-dimensional array ports. |
See also:
Creating a Block Symbol File for a Current File
|
- PLDWorld - |
|
|
| Created by chm2web html help conversion utility. |