| CAUSE: | In a Verilog Design File (.v) at the specified location, you used an `include compiler directive. However, the Quartus II software cannot open the specified Verilog Design File. This error may occur if both the design file and the included file are located in a lower-level directory instead of at the project root directory, if the included file is an encrypted megafunction design file for which you do not have a license, or if did not specify the correct file name or path name of the included Verilog Design File in the Include Statement. |
| ACTION: | Make sure that all design files are in the correct locations, that any megafunctions you reference are correctly licensed, and that you have spelled the file names and path names of included files correctly. Make sure all included files are either in the project root directory, or are referenced by their full path from the project root directory. |
See also:
Sections 13.2 and 19.5 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual
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