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Verilog HDL Case Statement error at <location>: must use no more than one Default Statement

CAUSE: In a Case Statement at the specified location in a Verilog Design File (.v), you have specified more than one Default Statement; however, you must specify no more than one Default Statement in a Case Statement.
ACTION: Remove the extra Default Statements from the Case Statement until it contains no more than one Default Statement.

See also:

Section 9.5 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

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