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Verilog HDL error at <location>: value cannot be assigned to constant


CAUSE: In a Verilog Design File (.v) at the specified location, you assigned a value to a constant wire; however, assignments to constants are not allowed. This error may occur if, for example, w is declared as wire [1:0] and you assign w[2] = 1;.
ACTION: Edit the design so the data type and bus width are correct and do not create an assignment to a constant.

See also:

Sections 2 and 6 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

- PLDWorld -

 

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