Quartus

Verilog HDL User-Defined Primitive Declaration error at <location>: rising or falling edge is not allowed in combinational user-defined primitive <name>

CAUSE: In the specified User-Defined Primitive (UDP) Declaration at the specified location in a Verilog Design File (.v), you used a rising or falling edge; however, rising or falling edges are not allowed in combinational UDPs.
ACTION: Edit the design to remove the rising or falling edge from the specified UDP.

See also:

Section 8 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

- PLDWorld -

 
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