Quartus

Verilog HDL Event Control Statement error at <location>: Event Control Statement must be inside of Always Construct or Initial Construct

CAUSE: In a Verilog Design File (.v) at the specified location, you used an Event Control Statement, but did not place it inside either an Always Construct or an Initial Construct. The Event Control Statement must always be inside either an Always Construct or an Initial Construct.
ACTION: Move the Event Control Statement into an Always Construct or an Initial Construct.

See also:

Section 9.7 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

- PLDWorld -

 
Created by chm2web html help conversion utility.