Quartus

Verilog HDL error at <location>: assignment to illegal expression


CAUSE: In a Verilog Design File (.v) at the specified location, you made an assignment to an illegal expression, or an expression that is not supported by the Quartus II software.
ACTION: Make sure the assigned expression is a legal expression.

See also:

Section 6 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

- PLDWorld -

 

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