| CAUSE: | In an Always Construct at the specified location in a Verilog Design File (.v), you used a Force Statement. Although Force Statements are supported in Verilog HDL, they are not supported for processing with Integrated Synthesis. A Force Statement is used in conjuction with a Release Statement to override values on wires or registers. It is typically used with a simulator during design debugging to change signal values; however, it is not supported for synthesis, because you should never need to release the value on a wire or in a net in a synthesized design. |
| ACTION: | Edit the design to remove the Force Statement. |
See also:
Sections 5.6.2 and 9.3 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual
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