| CAUSE: | In an Always Construct at the specified location in a Verilog Design File (.v), you used a Forever Statement. However, although Forever Statements are supported in both Always Constructs and Initial Constructs in Verilog HDL, the Quartus II sofware supports Forever Statements only in Initial Constructs. |
| ACTION: | Move the Forever Statement from the Always Construct to an Initial Construct, or replace the Forever Statement in the Always Construct with one of the other types of Looping Statements. |
See also:
Section 9.6 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual
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