CAUSE: | In a Verilog Design File (.v) at the specified location, you used a Function Call, but the Function Call does not pass the correct arguments to the function. The number of arguments passed must match the number of arguments in the Function Definition exactly. |
ACTION: | Edit the design to make sure the argument list in the Function Call matches the argument list in the Function Definition. |
See also:
Sections 4 and 10.3 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual
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