| CAUSE: | In a Generate Statement at the specified location in a Verilog Design File (.v), you used a name that is not is not declared as a Generate Statement index variable, or genvar. An index variable that is used to control a Generate Statement must be declared as a genvar. You cannot use other data types as Generate Loop variables. |
| ACTION: | Make sure each variable used to control a Generate Statement is declared as a genvar. |
See also:
Section 12.1.3 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual
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