| CAUSE: | In a Variable Declaration at the specified location in a Verilog Design File (.v), you declared a variable that had already been declared in the design. You must declare a variable only once in a design. |
| ACTION: | Remove the duplicate Variable Declaration from the design. |
See also:
Sections 3.2.2 and 6.2.1 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual
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