EVRFX_VERI_IF_CONDITION_DOES_NOT_MATCH_SENSITIVITY_LIST

Verilog HDL Conditional Statement error at <location>: If-Else Statement does not match any sensitivity list edge

CAUSE:

In a Conditional Statement at the specified location in a Verilog Design File (.v), you specified an If-Else Statement inside an Always Construct that does not match any edge on the sensitivity list of the Always Construct. This error may occur if you are trying to model a DFF with multiple control signals. The Quartus II software will only infer a secondary signal from a single secondary signal in an if condition. For example, you may have written the following sample structure to model a DFF primitive that can be reset by two signals, rst1 or rst2:

  always @ (posedge clk or posedge rst1 or posedge rst2)
  begin
    if (rst1 == 1'b1 || rst2 == 1'b1)
      q <= 1'b0;
    else
      q <= d;
  end

The Quartus II software will give an error for this sample Conditional Statement because it contains an expression with two sensitivity list edges.

ACTION:

Edit the design to specify only one edge per if condition. For example, if you were to edit the previous example to specify only one edge per if condition, the Quartus II software would then succesfully recognize the DFF primitive. The sample code would then appear as follows:

  always @ (posedge clk or posedge rst1 or posedge rst2)
  begin
    if (rst1 == 1'b1)
      q <= 1'b0;
    else if (rst2 == 1'b1)
      q <= 1'b0;
    else
      q <= d;
  end

Alternatively, you could generate the OR of rst1 and rst2 outside the Always Construct.

See also:

Section 9.4 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

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