Quartus

Verilog HDL syntax error at <location>: illegal character in binary number

CAUSE: In a Verilog Design File (.v) at the specified location, a binary number contains an illegal character.
ACTION: Make sure you use only 0 and 1 digits in binary numbers.

See also:

Section 2.5 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

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