| CAUSE: | In a Verilog Design File (.v) at the specified location, you used a binary operator with an integer variable; however, the operator you used is not supported for integers. |
| ACTION: | Edit the design to use a different variable type or to use a different operator. |
See also:
Section 4.1 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual
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