| CAUSE: | In a Verilog Design File (.v) at the specified location, you used a binary operator in a real number expression; however, the operator you used is not supported for real number expressions. Although, Integrated Synthesis supports arithmetic functions in real number expressions, it does not support bit-wise and logical operations in real number experessions. |
| ACTION: | Edit the design to use an integer or reg variable type if you require bit-wise operations. |
See also:
Section 4.1 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual
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