Quartus

Verilog HDL syntax error at <location>: illegal character in decimal number

CAUSE: In a Verilog Design File (.v) at the specified location, a decimal number contains an illegal character.
ACTION: Make sure you use only digits 0 through 9 in decimal numbers.

See also:

Section 2.5 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

- PLDWorld -

 
Created by chm2web html help conversion utility.