| CAUSE: | In a Verilog Design File (.v) at the specified location, you used an identifier in an expression, but the identifier does does not evaluate to a data type. For example, the identifier may be a module name. |
| ACTION: | Remove the specified identifier from the expression. |
See also:
Section 2.7 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual
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