Quartus

Verilog HDL error at <location>: variable <name> cannot be indexed because it is not declared as an array

CAUSE: In a Verilog Design File (.v) at the specified location, you indexed the specified variable, but the variable cannot be indexed because it is not declared as an array.
ACTION: Declare the variable as an array with the proper bit width.

See also:

Section 3.10 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

- PLDWorld -

 
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