Quartus

Verilog HDL For Statement error at <location>: loop count exceeds limit

CAUSE: In a For Statement at the specified location in a Verilog Design File (.v), you specified a termination condition for the For loop that is never false, which causes an infinite loop during expansion.
ACTION: Make sure the terminating condition and assignment for the For loop are correct.

See also:

Section 9.6 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

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