Quartus

Verilog HDL User-Defined Primitive Declaration error at <location>: inout ports are not allowed on UDP

CAUSE: In a User-Defined Primitive (UDP) Declaration at the specified location in a Verilog Design File (.v), you specified an inout port; however, a UDP cannot use the inout port type. Only input and output ports are allowed for UDPs.
ACTION: Edit the UDP port declarations so they specify only input and output ports.

See also:

Section 8.1 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

- PLDWorld -

 
Created by chm2web html help conversion utility.