Quartus

Verilog HDL error at <location>: illegal name <name> used in expression

CAUSE: In a Verilog Design File (.v) at the specified location, you used a name in an expression, but the name is not legal for use in the expression. For example, this error may occur if you instantiate a module, and then try to assign the instantiated module to another signal, as shown in the following example:
sub sub_inst (in1, in2, temp);	
assign out = sub_inst;
ACTION: Remove the specified name from the expression.

See also:

Section 4 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

- PLDWorld -

 
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