EVRFX_VERI_MEMORY

Verilog HDL error at <location>: memory cannot be accessed directly

CAUSE:

In an Always Construct, at the specified location in a Verilog Design File (.v), you declared an array for direct memory access; however, memory must not be accessed directly.

ACTION:

Specify access to the memory explicitly, bit by bit, as shown in the following example:

module mem_fixed(x);
output [1:0] x;
reg mem1bit[1:0];
always
begin
    x[1] = mem1bit[1];
    x[0] = mem1bit[0];
end
endmodule

See also:

Section 3.10 and 4.2 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

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