EVRFX_VERI_MEMORY

Verilog HDL error at <location>: values cannot be assigned directly to memory <name>

CAUSE:

In a Verilog Design File (.v) at the specified location, you assigned values directly to the specified memory, but you must not assign values to an entire memory directly.

ACTION:

Assign values explictly to individual memory bits, as shown in the following example:

module mem_fixed(a, x);
input [1:0] a;
output x;
reg mem1bit[1:0];
always
begin
    mem1bit[1] = a[1];
    mem1bit[0] = a[0];
end
endmodule

See also:

Section 6.2 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

- PLDWorld -

Created by chm2web html help conversion utility.