| CAUSE: | In a Verilog Design File (.v) at the specified location, you used a text macro name that has no arguments; however, the Text Macro Definition does have arguments. The number of arguments in the call to the macro must match the number of arguments in the Text Macro Definition. |
| ACTION: | Edit the design to make sure the number of arguments in the macro name match the number of arguments in the Text Macro Definition. |
See also:
Section 19.3 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual
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