Quartus

Verilog HDL error at <location>: variable <name> has mixed blocking and nonblocking Procedural Assignments -- must be all blocking or all nonblocking assignments

CAUSE: In a Verilog Design File (.v) at the specified location, you made both blocking and nonblocking Procedural Assignments to one variable in the same Always Construct. Procedural Assignments to the same variable must either all be blocking or all be nonblocking.
ACTION: Change or delete one or more assignments so that the Procedural Assignments for the variable are either all blocking or all nonblocking.

See also:

Section 6 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

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