| CAUSE: | In a Gate Instantiation at the specified location in a Verilog Design File (.v), you instantiated a built-in logic gate; however, the gate is missing required ports. Basic logic gates require at least one input and one output connection to function correctly in the circuit. |
| ACTION: | Add the missing input or output ports to the gate. |
See also:
Section 7.1 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual
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