| CAUSE: | In a Verilog Design File (.v) at the specified location, you used a Gate Instantiation for a predefined logic gate; however, the logic gate is not using the expected number of input and output ports. The gate requires the specified number of connections to function correctly in the design. |
| ACTION: | Check the port syntax in the Gate Instantiation and adjust the connection list accordingly. |
See also:
Section 7.1 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual
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