Quartus

Verilog HDL error at <location>: part-select has negative size, but must use zero or more bits

CAUSE: In a Verilog Design File (.v) at the specified location, you have used a part-select of a vector with a negative size. However, the part-select must select at least zero or more bits.
ACTION: Make sure all part-selects in the design select a partial array of zero or more bits of their vector.

See also:

Section 3.10 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

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