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Verilog HDL For Statement error at <location>: must use only constant expressions in terminating conditions

CAUSE: In a For Statement at the specified location in a Verilog Design File (.v), you specified a terminating condition for a For loop that contains an arbitrary limit variable; however, only constant expressions are supported in For loop conditions.
ACTION: Make sure the terminating condition for the For loop contains only constant expressions.

See also:

Section 9.6 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

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