Quartus

Verilog HDL error at <location>: variable <name> is not synthesizable because it does not hold its value under NOT (clock-edge) conditions

CAUSE: In a Verilog Design File (.v) at the specified location, you used the specified variable, but the variable is not synthesizable because it does not hold its value under NOT (clock-edge) conditions.
ACTION: Remove any code that assigns a value to the variable when the clock is not rising or falling.

See also:

Section 6.2 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

- PLDWorld -

 
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