CAUSE: | In a Verilog Design File (.v) at the specified location, you assigned a value directly to a nonvariable; however, a value must not be assigned to a nonvariable. |
ACTION: | Remove the assignment or create a new variable for the assignment. |
See also:
Section 6.2 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual
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