EVRFX_VERI_OPPOSITE

Verilog HDL error at <location>: part-select direction is opposite from prefix index direction

CAUSE:

In a Verilog Design File (.v) at the specified location, you used a part-select to select a part of a vector; however, in the part-select, the direction from MSB to LSB is reversed from the direction in the declaration of the vector. For example, see the following excerpt of a sample design, which uses a part-select on vector:

module veri_test(in, out);
	input [3:0] in;
	output [1:0] out;
	assign out = in[0:1];
	endmodule

ACTION:

Use the same direction in the part-select of a vector as is used in the declaration of the vector. For example, in the previous sample design, you can change the assignment to out into the following format:

assign out = in[1:0];

See also:

Section 4 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

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