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Verilog HDL Module Declaration error at <location>: can't override parameters -- module does not expect any parameters

CAUSE: In a Module Declaration at the specified location in a Verilog Design File (.v), you specified a Module Instance Parameter Value Assignment to override one or more specified paramters for the instance; however, no parameters have been defined for the module.
ACTION: Edit the Module Declaration to define parameters, or edit or remove the parameter overrides that are specified in the Module Instance Parameter Value Assignment.

See also:

Section 12.1 and 12.2 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

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