| CAUSE: | In a Verilog Design File (.v) at the specified location, you used a Defparam Statement or a named Module Instance Parameter Value Assignment list to change the value of a parameter in a module that you are instantiating. However, the specified parameter does not exist in the instantiated module. This error may occur if you have mistyped the parameter name. |
| ACTION: | Carefully check the names in the Parameter Value Assignment Statement and in the instantiated module to make sure they match. |
See also:
Section 12 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual
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