Quartus

Verilog HDL error at <location>: variable <name> cannot be part-selected because it is not declared as an array

CAUSE: In a Verilog Design File (.v) at the specified location, you used a part-select for the specified variable, but the variable cannot be part-selected because it is not declared as an array.
ACTION: Declare the variable as an array with the proper bit width.

See also:

Sections 3.10 and 4.2.1 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

- PLDWorld -

 
Created by chm2web html help conversion utility.