Quartus

Verilog HDL Module Declaration error at <location>: port <name> is not declared as port

CAUSE: In a Module Declaration at the specified location in a Verilog Design File (.v), you specified a port name, but the specified port name is not declared as a port.
ACTION: Declare the port as an input, output, or bidirectional port.

See also:

Section 12.1 and 12.3 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

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