| CAUSE: | In a Reg Declaration at the specified location in a Verilog Design File (.v), you declared the specified variable as a reg data type; however, the variable was previously declared as a net data type in a Net Declaration. The variable must be declared as only one data type. |
| ACTION: | Remove either the Net Declaration or the Reg Declaration. |
See also:
Sections 3.2.1 and 12.3.3 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual
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