Quartus

Verilog HDL User-Defined Primitive Declaration error at <location>: user-defined primitive must have only one output port

CAUSE: In a User-Defined Primitive (UDP) Declaration at the specified location in a Verilog Design File (.v), you specified a UDP with more than one output port; however, a UDP must have only one output port.
ACTION: Make sure the UDP has only one output port.

See also:

Section 8 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

- PLDWorld -

 
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