Quartus

Verilog HDL Compiler Directive error at <location>: text macro <name> is same as predefined text macro

CAUSE: In a Text Macro Defintion at the specified location in a Verilog Design File (.v), you defined a text macro name that is the same name as a predefined text macro.
ACTION: Define the text macro using a different name.

See also:

Section 19.3 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

- PLDWorld -

 
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