Quartus

Verilog HDL syntax error at <location>: syntax error near text '<text>'

CAUSE: In a Verilog Design File (.v) at the specified location, a syntax error occurred near the specified text. For example, this error may occur if required punctuation, such as a semicolon or parenthesis, is missing before the specified text.
ACTION: Check for and fix any syntax errors that appear immediately before or at the specified keyword.

See also:

Section 6.2.1 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

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