CAUSE: | In a Verilog Design File (.v), a syntax error occurred near the end of the file. For example, this error may occur if required punctuation, such as a semicolon or parenthesis, is missing at the end of the file. |
ACTION: | Check for and fix syntax errors at the end of the file. |
- PLDWorld - |
|
Created by chm2web html help conversion utility. |